A gate array typically includes an inner core cell area which is comprised of a plurality of cells. Each of the plurality of cells include a plurality of transistors. A gate array designed in this fashion is typically referred to as a sea of cells gate array or a sea of transistors gate array.
Typically, sea of cells gate arrays are implemented with a core cell which includes both PMOS and NMOS transistors all of which are substantially equal in size. However, this structure limits the capability of the gate array to implement efficient and stable memory structures. Moreover, such a structure also limits the flexibility to make speed/power/area tradeoffs when constructing logic macros. For example, if only one transistor size is available, it becomes difficult to balance rising and falling propagation delays or to manage dynamic power dissipation.
Hence, there exists a need for an improved gate array architecture having a core cell which is both memory and logic efficient.